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ADC data corruptiom

Question asked by kilshtein.daniel on Apr 25, 2013
Latest reply on Apr 28, 2013 by Clive One

I have some strange behavior with ADC conversions.
Here is a short description of the whole system:
ADC3 with DMA2_Stream0 sampling a single channel at 250KHz in a double buffer mode with an external trigger (timer 3)
ADC1 with DMA2_Stream4 sampling two channels at 1KHz in a with an external trigger (timer 2)
DCMI with DMA2_Stream1   - QVGA image triggered by the DMA_IT_TC interrupt.
I also have another device connected to an I2C bus and all data is stored on the SD card.
i dont use

Since my system is heavily loaded, I get the ADC_IT_OVR on the ADC3 from time to time. The problem is that since ADC3 is in a double buffer mode,
I cannot just clear the ADC_IT_OVR flag and I have to re-initialize both DMA and the ADC (as described in zzzz)
after I do that, I get a lot of noise inside on my pictures (sample picture attached).I don’t mind to loss a few ADC3 sample and I was wondering,
Is there a way to tell the ADC to ignore the ADC_IT_OVR error (it happens even if the ADC_IT_OVR interrupt is not set by the ADC_ITConfig function).

Here is the code for both ADCs initialization and both interrupt handllers:

static void ADC1_HwInit(void)
{
  ADC_InitTypeDef               ADC_InitStructure;
  DMA_InitTypeDef               DMA_InitStructure;
  TIM_TimeBaseInitTypeDef       TIM_TimeBaseStructure;
  GPIO_InitTypeDef              GPIO_InitStructure;  
  NVIC_InitTypeDef              NVIC_InitStructure;

  //Enable RCC
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2 | RCC_AHB1Periph_GPIOA, ENABLE);  
  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
    
  TIM_TimeBaseStructure.TIM_Prescaler = (SystemCoreClock / 10000000) - 1;// 1 MHz
  TIM_TimeBaseStructure.TIM_Period = 5000 - 1;                     //1MHz /25 = 400KHz
  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
  TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
  TIM_SelectOutputTrigger (TIM2, TIM_TRGOSource_Update);
  TIM_ARRPreloadConfig(TIM2, ENABLE);
    
  // DMA2_Stream4 channel0
  DMA_DeInit(DMA2_Stream4);
  DMA_InitStructure.DMA_Channel = DMA_Channel_0;  
  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADC1_DR_ADDRESS;
  DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)ADC1_FSMC_SRAM_ADDRESS;
  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
  DMA_InitStructure.DMA_BufferSize = adc1_BufferSize;
  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
  DMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
  DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;         
  DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
  DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
  DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
  DMA_Init(DMA2_Stream4, &DMA_InitStructure);
  DMA_Cmd(DMA2_Stream4, ENABLE);
   
  //IOs
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
  GPIO_Init(GPIOA, &GPIO_InitStructure);
 
  //ADC 1
  ADC_InitStructure.ADC_Resolution = ADC_Resolution_8b;
  ADC_InitStructure.ADC_ScanConvMode = ENABLE;
  ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
  ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_Rising;
  ADC_InitStructure.ADC_ExternalTrigConv     = ADC_ExternalTrigConv_T2_TRGO;
  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
  ADC_InitStructure.ADC_NbrOfConversion = 2;
  ADC_Init(ADC1, &ADC_InitStructure);
  ADC_DMACmd(ADC1, ENABLE);
 
  ADC_RegularChannelConfig(ADC1, ADC_Channel_0, 1, ADC_SampleTime_15Cycles);
  ADC_RegularChannelConfig(ADC1, ADC_Channel_1, 2, ADC_SampleTime_15Cycles);

  // Enable DMA request after last transfer (Single-ADC mode)
  ADC_DMARequestAfterLastTransferCmd(ADC1, ENABLE);
      
  ADC_ITConfig(ADC1, ADC_IT_OVR , ENABLE);
   
  DMA_ITConfig(DMA2_Stream4, DMA_IT_TC | DMA_IT_TE , ENABLE);
 
  //start!!!
  TIM_Cmd(TIM2, ENABLE);
  ADC_Cmd(ADC1, ENABLE);
  ADC_SoftwareStartConv(ADC1);
}


void ADC3_HwInit(void)
{
  ADC_InitTypeDef       ADC_InitStructure;
  DMA_InitTypeDef       DMA_InitStructure;
  GPIO_InitTypeDef      GPIO_InitStructure;
  TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
  NVIC_InitTypeDef  NVIC_InitStructure;
 
  //Enable ADC3, DMA2, Timer and GPIO clocks
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2 | RCC_AHB1Periph_GPIOF , ENABLE);
  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE);
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
    
  TIM_TimeBaseStructure.TIM_Prescaler = (SystemCoreClock / 10000000) - 1;//1 MHz
  TIM_TimeBaseStructure.TIM_Period = 20 - 1;                   
  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
  TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
  TIM_SelectOutputTrigger (TIM3, TIM_TRGOSource_Update);
  TIM_ARRPreloadConfig(TIM3, ENABLE);
 
  //IOs
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
  GPIO_Init(GPIOF, &GPIO_InitStructure);
 
  //ADC_DeInit();
  ADC_InitStructure.ADC_Resolution = ADC_Resolution_8b;
  ADC_InitStructure.ADC_ScanConvMode = DISABLE;
  ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
  ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_Rising;
  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
  ADC_InitStructure.ADC_NbrOfConversion = 1;
 
  ADC_InitStructure.ADC_ExternalTrigConv     = ADC_ExternalTrigConv_T3_TRGO;
  ADC_Init(ADC3, &ADC_InitStructure);

  /* ADC3 regular channel7 configuration *************************************/
  ADC_RegularChannelConfig(ADC3, ADC_Channel_7, 1, ADC_SampleTime_15Cycles);
 
 /* Enable DMA request after last transfer (Single-ADC mode) */
  ADC_DMARequestAfterLastTransferCmd(ADC3, ENABLE);
    
  ADC_ITConfig(ADC3, ADC_IT_OVR , ENABLE);
 
  //DMA2 Stream1 Configuration
  DMA_DeInit(DMA2_Stream0);
  DMA_InitStructure.DMA_Channel = DMA_Channel_2;
  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADC3_DR_ADDRESS;    
  DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)ADC3_FSMC_SRAM_ADDRESS0;
  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
  DMA_InitStructure.DMA_BufferSize = adc3_BufferSize;
  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
  DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
  DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
  DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;

  DMA_DoubleBufferModeConfig(DMA2_Stream0, (uint32_t)ADC3_FSMC_SRAM_ADDRESS0 +  adc3_BufferSize, DMA_Memory_0);
  DMA_DoubleBufferModeCmd(DMA2_Stream0, ENABLE);

  DMA_ITConfig(DMA2_Stream0, DMA_IT_TC , ENABLE);
 
  DMA_Init(DMA2_Stream0, &DMA_InitStructure);
 
  //Start
  ADC_DMACmd(ADC3, ENABLE);
  ADC_Cmd(ADC3, ENABLE);
  TIM_Cmd(TIM3, ENABLE);
  DMA_Cmd(DMA2_Stream0, ENABLE);

  ADC_SoftwareStartConv(ADC3);
}

void ADC_IRQHandler()
{
  DMA_InitTypeDef       DMA_InitStructure;
   
  if(ADC_GetITStatus(ADC1, ADC_IT_OVR) != RESET)
  {
    ADC_ClearFlag(ADC1, ADC_FLAG_OVR);
  }
  if(ADC_GetITStatus(ADC3, ADC_IT_OVR) != RESET)
  {
    ADC3_HwInit();
    ADC_ClearFlag(ADC3, ADC_FLAG_OVR);
  }
}


void DMA2_Stream0_IRQHandler(void)
{
  portBASE_TYPE Adc3TaskWoken = pdFALSE;
 
  // Transfer complete interrupt
  if (DMA_GetFlagStatus(DMA2_Stream0, DMA_FLAG_TCIF0) != RESET)
  {
    DMA_ClearFlag(DMA2_Stream0, DMA_FLAG_TCIF0);   
    DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_TCIF0);
      // Give the semaphore to wakeup camera blocking task
      if( Adc3_xSemaphore != NULL)
      {
        xSemaphoreGiveFromISR(Adc3_xSemaphore, &Adc3TaskWoken);
        if (Adc3TaskWoken != pdFALSE)
        {
          portEND_SWITCHING_ISR(Adc3TaskWoken);
        }
      }
  }
 
  if (DMA_GetFlagStatus(DMA2_Stream0, DMA_FLAG_TEIF0) != RESET)
  {
    DMA_ClearFlag(DMA2_Stream0, DMA_FLAG_TEIF0);
    DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_TEIF0);
  }
    
  if (DMA_GetFlagStatus(DMA2_Stream0, DMA_FLAG_HTIF0) != RESET)
  {
    DMA_ClearFlag(DMA2_Stream0, DMA_FLAG_HTIF0);
    DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_HTIF0);
  }
 
}


void DMA2_Stream4_IRQHandler(void)
{
  portBASE_TYPE Adc1TaskWoken = pdFALSE;
 
   // Transfer complete interrupt
  if (DMA_GetFlagStatus(DMA2_Stream4, DMA_FLAG_TCIF4) != RESET)
  {
    // Clear the Interrupt flag
    DMA_ClearFlag(DMA2_Stream4, DMA_FLAG_TCIF4);
       
    // Give the semaphore to wakeup camera blocking task
    if( Adc1_xSemaphore != NULL)
    {
      xSemaphoreGiveFromISR(Adc1_xSemaphore, &Adc1TaskWoken);
      if (Adc1TaskWoken != pdFALSE)
      {
        portEND_SWITCHING_ISR(Adc1TaskWoken);
      }
    }
  }
 
  else if (DMA_GetFlagStatus(DMA2_Stream4, DMA_FLAG_HTIF4) != RESET)
  {
    DMA_ClearFlag(DMA2_Stream4, DMA_FLAG_HTIF4);
    DMA_ClearITPendingBit(DMA2_Stream4, DMA_IT_HTIF4);
  }
 
  else if (DMA_GetFlagStatus(DMA2_Stream4, DMA_FLAG_TEIF4) != RESET)
  {
    DMA_ClearFlag(DMA2_Stream4, DMA_FLAG_TEIF4);
  }

}



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