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External SRAM 16-bit access - elucidation required [SOLVED]

Question asked by johsey on Apr 19, 2013
Latest reply on Apr 19, 2013 by johsey

I've doubts regarding the access of an external SRAM (IS61WV102416BLL) connected to the FSMC bus that has the following specifications. This SRAM is organized as 1024K x 16-bit.

My assumption is, by using the following code (SRAM is mapped to 0x64000000), I would be able to access two consecutive half-words (16-bit wide):

1.volatile uint16_t * p_sram_1 = (volatile uint16_t *)0x64000000;
2.volatile uint16_t * p_sram_2 = (volatile uint16_t *)0x64000001;
4.*p_sram_1 = 0xBBAA;
5.*p_sram_2 = 0xDDCC;
7.uint16_t data1 = *p_sram_1;
8.uint16_t data2 = *p_sram_2;

I expect that data1 will contain 0xBBAA and data2, 0xDDCC. But when I execute this code, data1 contains 0xCCAA instead of 0xBBAA. This let me think that each address accesses one byte instead of two bytes that I expected.

Am I totally wrong with my expectations or is the FMSC bus translating unaligned addresses accesses in upper byte or lower byte accesses?

Thank you for your help.