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Ethernet problems @ 10Mbit/s half duplex with STM32F207IG and KSZ8863RLL PHY.

Question asked by heinrich.damien on Apr 5, 2013
Latest reply on Mar 27, 2018 by Michał Pełka
Hello everyboby,

I'm using KSZ8863RLL chip from Micrel as Ethernet PHY, with STM32F207IG in RMII mode.
50 MHz Clock reference is sourced externally by an oscillator.
PHY registers are accessed through SMI (with ETH_MACMIIAR and ETH_MACMIIDR registers). This interface is known as MIIM or MDIO interface on PHY's side.
Moreover, I'm using uC/OS-III with uC/TCP-IP stack.

I'm facing issues in 10 Mbit/s half duplex configuration, whereas everything is working well in 100 Mbit/s full duplex.
I can communicate at any time with PHY registers. The PHY auto-negotiation detects well the 10 Mbit/s network, PHY's status registers are correctly set (10 half capable). That information is properly recovered by STM32 which configures consequently FES and DM bits of ETH_MACCR. From this point, no DMA Rx IT is occuring anymore, whereas it's correctly happening in 100 Mbit/s.
I have reset ROD bit (Receive own disable) in ETH_MACCR, but my issue is still present.
I have checked every configuration registers, IT mask registers, and everything is looking fine.
I have scoped TXD and RXD, and it seems to be traffic on it, even if I'm not a specialist of RMII protocol.

I'm quite disappointed, I can't even determinate if that problem come from STM32 side, PHY side, or other reason like clock source.
I have looked for similar issue on STe2eCommunities without any success...

Has someone maybe a lead to follow ?


Thanks in advance,
Best regards,

Damien

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