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RCC_CFGR_HRPE Bit? (SysClk Devider)

Question asked by bil.til on Mar 28, 2013
Latest reply on Mar 28, 2013 by waclawek.jan
Hi,
in the file System_ST32F4xx.c of the ST4Discovery examples, I always find the following 2 lines for the clock configuration (SysClk 168MHz):
    /* HCLK = SYSCLK / 1*/
    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
      
    /* PCLK2 = HCLK / 2*/
    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
    
    /* PCLK1 = HCLK / 4*/
    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;

I understand the meaning for the last 4 lines - here SysClk must be devided by 2 or 4, resp., as the APB1 and APB2 frequencies are limited to 84MHz and 42MHz.

But concerning the first 2 lines, here the RM 6.3.3(RCC_CFGR) states:
Bits 7:4 HPRE: AHB prescaler
Set and cleared by software to control AHB clock division factor. ...
0xxx: system clock not divided
1000: system clock divided by 2
...

So according to this register description, RCC_CFGR_HRPE could be left on its init value of 0. Why is it programmed to the value "2" in the ST4Discovery examples? Anyone has any idea?


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