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NVIC and invalid SCB->ICSR register with DMA2

Question asked by Jack Peacock on Mar 14, 2013
Latest reply on May 21, 2013 by Jack Peacock
Environment is an STM32F205VF on a custom board, but the problem has also appeared on a STM3240G eval board with an STM32F407I.  Compiler is GCC 4.6.2 at optimize level O0 for debugging.

My application has extensive interrupt fault checking to detect a spurious interrupt request (IRQ) due to software or vector table errors.  I use the ICSR register to obtain the active IRQ when an interrupt service routine starts to verify the vector matches the interrupt request.  I have encountered a seemingly random event where the ICSR does not match the interrupt vector (for example, ICSR reports IRQ 44, CAN1 RX1, but the service routine vector is for DMA2 Stream 7, IRQ 93).  The vector table entries are correct.

I use DMA to transmit data out to USART1 on DMA2 stream 7, which is working.  The DMA service routine triggers on a TC at end of transmit.  The invalid ICSR IRQ occurs rarely, perhaps once an hour, which would imply some type of race conditon.  I'm at a loss to explain how the ICSR can report an active request for an interrupt which is not enabled.  I verified the NVIC settings: the CAN peripheral is not enabled and no NVIC interrupts for the CAN are enabled.  In any case the ICSR should not report an active CAN request after entering a DMA interrupt service routine.  I have two active DMA2 streams: USART1 TX uses stream 7, and ADC1 uses DMA2 stream 4.

I have not seen this behavior on the STM32F1xx series, so I suspect it may be related to the known problems with the DMA2 controller on STM32F2 and F4 parts, although this issue is not mentioned in the latest errata.  My theory is it may be related to tail-chaining, where the same service routine is triggered a second time while being serviced, but the ICSR is invalid on the second call.

Does anyone use the ICSR register in the SCB to check interrupt vectors?  Is the invalid ICSR an ARM problem or ST?
  Jack Peacock

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