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STM32F4xx interfacing NAND

Question asked by valdes.alejandro on Mar 1, 2013
Latest reply on Mar 13, 2013 by valdes.alejandro
Hi

Frustration growing, trying to interface a NAND (Micron MT29F4G...) ... seem pretty straight forward specially after all the examples available online. After sending the RESET Command (0xff), I tried issuing a CMD_READ_STATUS (0x70) and right after the write the whole debugger crashes and only solution is power down power up board.

Below is the initialization of the FSMC for NAND operation the Chip select is that of Back 3.

#define FSMC_Bank_NAND   FSMC_Bank3_NAND
/* PORT D */
#define NAND_CLE        GPIO_Pin_11         /* FSMC */
#define NAND_CLE_s      GPIO_PinSource11    /* FSMC */
#define NAND_ALE        GPIO_Pin_12         /* FSMC */
#define NAND_ALE_s      GPIO_PinSource12    /* FSMC */
#define NAND_D0         GPIO_Pin_14         /* FSMC */
#define NAND_D0_s       GPIO_PinSource14    /* FSMC */
#define NAND_D1         GPIO_Pin_15         /* FSMC */
#define NAND_D1_s       GPIO_PinSource15    /* FSMC */
#define NAND_D2         GPIO_Pin_0          /* FSMC */
#define NAND_D2_s       GPIO_PinSource0     /* FSMC */
#define NAND_D3         GPIO_Pin_1          /* FSMC */
#define NAND_D3_s       GPIO_PinSource1     /* FSMC */
#define NAND_NOE        GPIO_Pin_4          /* FSMC */
#define NAND_NOE_s      GPIO_PinSource4     /* FSMC */
#define NAND_NWE        GPIO_Pin_5          /* FSMC */
#define NAND_NWE_s      GPIO_PinSource5     /* FSMC */
#define NAND_NWAIT      GPIO_Pin_6          /* FSMC */
#define NAND_NWAIT_s    GPIO_PinSource6     /* FSMC */
//#define NAND_NCE2   GPIO_Pin_7  /* FSMC when BANK 2 is used */
/* PORT E */
#define NAND_D4         GPIO_Pin_7          /* FSMC */
#define NAND_D4_s       GPIO_PinSource7     /* FSMC */
#define NAND_D5         GPIO_Pin_8          /* FSMC */
#define NAND_D5_s       GPIO_PinSource8     /* FSMC */
#define NAND_D6         GPIO_Pin_9          /* FSMC */
#define NAND_D6_s       GPIO_PinSource9     /* FSMC */
#define NAND_D7         GPIO_Pin_10         /* FSMC */
#define NAND_D7_s       GPIO_PinSource10    /* FSMC */
/* PORT G */
#define NAND_NCE3       GPIO_Pin_9          /* FSMC when BANK 3 is used */
#define NAND_NCE3_s     GPIO_PinSource9     /* FSMC when BANK 3 is used */


void NAND_Init (void)
{
    GPIO_InitTypeDef GPIO_InitStructure; 
    FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
    FSMC_NAND_PCCARDTimingInitTypeDef  p;
   
    /* Clock to the IOs that are involved in the FSMC module */
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | 
                           RCC_AHB1Periph_GPIOG, ENABLE);    
    
    /* Enable FSMC clock */
    RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);    
    
    /* some default values */
    GPIO_StructInit (&GPIO_InitStructure);
    /*-- GPIO Configuration OUTPUT Lines -----------------------------*/
    /*!< CLE, ALE, D0->D3, NOE, NWE and NCE2  NAND pin configuration  */
    /* GPIOD configuration */
    GPIO_PinAFConfig(GPIOD, NAND_CLE_s, GPIO_AF_FSMC);
    GPIO_PinAFConfig(GPIOD, NAND_ALE_s, GPIO_AF_FSMC);
    GPIO_PinAFConfig(GPIOD, NAND_D0_s, GPIO_AF_FSMC);
    GPIO_PinAFConfig(GPIOD, NAND_D1_s, GPIO_AF_FSMC);
    GPIO_PinAFConfig(GPIOD, NAND_D2_s, GPIO_AF_FSMC);
    GPIO_PinAFConfig(GPIOD, NAND_D3_s, GPIO_AF_FSMC);
    GPIO_PinAFConfig(GPIOD, NAND_NOE_s, GPIO_AF_FSMC);
    GPIO_PinAFConfig(GPIOD, NAND_NWE_s, GPIO_AF_FSMC); 
    //GPIO_PinAFConfig(GPIOD, NAND_NWAIT_s, GPIO_AF_FSMC);
    GPIO_PinAFConfig(GPIOD, NAND_NWAIT_s, GPIO_AF_SDIO);
    
    GPIO_InitStructure.GPIO_Pin =  NAND_CLE | NAND_ALE | NAND_D0 | NAND_D1 |  
                                   NAND_D2 | NAND_D3 | NAND_NOE | NAND_NWE /*NAND_NWAIT*/;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;    /* FSMC, Alternate function */    
    /* configure */
    GPIO_Init(GPIOD, &GPIO_InitStructure); 
 
    GPIO_InitStructure.GPIO_Pin =  NAND_NWAIT;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;    /* As an input */    
    /* configure */
    GPIO_Init(GPIOD, &GPIO_InitStructure);
 
    /*!< D4->D7 NAND pin configuration  */  
    GPIO_PinAFConfig(GPIOE, NAND_D4_s, GPIO_AF_FSMC);
    GPIO_PinAFConfig(GPIOE, NAND_D5_s, GPIO_AF_FSMC);
    GPIO_PinAFConfig(GPIOE, NAND_D6_s, GPIO_AF_FSMC);
    GPIO_PinAFConfig(GPIOE, NAND_D7_s, GPIO_AF_FSMC);
    
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;    /* FSMC, Alternate function */  
    GPIO_InitStructure.GPIO_Pin = NAND_D4 | NAND_D5 | NAND_D6 | NAND_D7;    
    /* configure */
    GPIO_Init(GPIOE, &GPIO_InitStructure);
    
    /*!< Chip select for FSMC Bank 3 */  
    GPIO_PinAFConfig(GPIOG, NAND_NCE3_s, GPIO_AF_FSMC);
    GPIO_InitStructure.GPIO_Pin = NAND_NCE3;    
    /* configure */
    GPIO_Init(GPIOG, &GPIO_InitStructure);
 
    /*-- FSMC Configuration ------------------------------------------------------*/
    FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
    FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
    FSMC_NANDStructInit (&FSMC_NANDInitStructure);
    /* overwrite defaults */
    p.FSMC_SetupTime = 0x0;
    p.FSMC_WaitSetupTime = 0x2;
    p.FSMC_HoldSetupTime = 0x1;
    p.FSMC_HiZSetupTime = 0x0;
    /* NAND is connected to Bank 3 Chip Select */
    FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank3_NAND;
    FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
    FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
    /* NAND in used has built in ECC, 5 bit detection and 4 bit correction */
    FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Disable;    
    FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
    FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
    /* Commit the FSMC settings */ 
    FSMC_NANDInit(&FSMC_NANDInitStructure);
 
    /*!< FSMC NAND Bank Cmd Test */
    FSMC_NANDCmd(FSMC_Bank_NAND, ENABLE);
}

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