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Confused with USB FIFO Allocation

Question asked by xol.xol on Feb 25, 2013
Latest reply on Feb 26, 2013 by xol.xol
This is a piece of code from usb_core.c

/* set Rx FIFO size */
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);
 
/* EP0 TX*/
nptxfifosize.b.depth     = TX0_FIFO_FS_SIZE;
nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;
USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );

It allocates RX_FIFO_FS_SIZE for RX_FIFO and starts EP0 TX FIFO at 
nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;

But according to reference manual DIEPTXF0_HNPTXFSIZ is allocated in 32-bit words. So actually RX_FIFO_FS_SIZE*4 were allocated and thus TX0 FIFO should start at RX_FIFO_FS_SIZE*4 address. 

Where a bug is? Is it in source code or in reference manual?

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