AnsweredAssumed Answered

Unexpected I2C Status value of 0x84

Question asked by KernelSanders on Feb 15, 2013
I am receiving an unexpected status value from within my I2C ISR.
The value is 0x84 (TXE and BTF bits set). For now, I am only doing i2c master transmits, (I have a multimaster config but the other slave is not sending anything right now).
 According to the i2c header file, I should be getting these interrupts when doing a transmit...

I2C_EVENT_MASTER_MODE_SELECT
I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
I2C_EVENT_MASTER_BYTE_TRANSMITTED

I am using DMA for the transfer so I also receive the DMA IRQ. My transactions all succeed and will continue transmitting at a 1 second interval for several minutes, but, at some point, I get into the ISR and my breakpoint hits for an unknown interrupt value, 0x84.
Does anyone know what that status means?
Here is my code with the RX stuff (#defined 0 for now) taken out to show what I am expecting for a TX.

void I2C1_EVHandler(void)
{
   portBASE_TYPE   higherPriorityTaskWoken = pdFALSE;
   uint32_t        i2cStatus;
   uint8_t         receivedByte;
   uint32_t       count=0;

   i2cStatus = I2C_GetLastEvent(I2C1);

   if (i2cStatus == I2C_EVENT_MASTER_MODE_SELECT) /* Start Bit Sent*/
   {
        I2C1->DR = (sg_transmitI2cAddress << 1) & 0xFE;
   }
   else if (i2cStatus == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)
   {
      I2C_ITConfig(I2C1, I2C_IT_BUF | I2C_IT_EVT, DISABLE);
      //  Enable the TX DMA 
      I2CTxDmaChannel(pTxBuff, numBytes);
      I2C_DMACmd(I2C1, ENABLE);
   }
    else if (i2cStatus == I2C_EVENT_MASTER_BYTE_TRANSMITTED) /* Transaction Complete */
   {
 
      I2C_GenerateSTOP(I2C1, ENABLE);
   }
   else
   {
       count++; 
   }
     portEND_SWITCHING_ISR(higherPriorityTaskWoken);
}

Edit:
I see in the documentation that it is an expected case, but why would I get a periodic interrupt because of it? I transmit hundreds of transactions before I hit this case. The documentation says that this is cleared by the STOP condition, but it isn't. I'll keep reading and debugging but any help is appreciated.

 

Figure 237. Transfer sequence diagram for master transmitter

 

 8_2:  TxE=1, BTF = 1, Program Stop request. TxE and BTF are cleared by hardware by the Stop condition

 

Outcomes