I am using DMA to transfer data to/from an EEPROM over I2C. Most of the time this is working fine but on the odd occasion when reading from the EEPROM the I2C peripheral does not seem to be sending a NACK when the last byte has been DMA’d, despite the “LAST” bit being set in the I2C_CR2 register.
Using a storage oscilloscope, the trace clearly shows that most of the time an ACK is sent after each byte and a NACK is sent after the last byte. However, occasionally it shows an ACK being sent after the last byte instead of a NACK. This causes the EEPROM to remain in a BUSY state, expecting more data to be read. No clock cycles are provided by the micro because the DMA has completed. It behaves as if the “LAST” bit in the I2C_CR2 register is not always working.
Is this a known problem? Is there “interference” with the DMA operation from other peripherals in the micro? Is there a workaround?