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I2S and variable sampling rate

Question asked by K A on Nov 22, 2012
Latest reply on Nov 22, 2012 by K A

I have fully working I2S with external codec (TLV320AIC23). I have decided to save a
crystal and feed the clock to the codec from the I2C pll. So according to the codec pdf this
clock needs to be constant (say 12.288 Mhz) and sampling rate is changed via SPI/I2C
command. Then the STM32 pdf says that the I2S output clock is based on the sampling
rate (256 * Fs). In practice changing the sampling rate when making init of the I2S will
change the divider values and correct clock will be available only at 48 kHz. With
8 kHz sampling rate the clock will drop as low as 2 Mhz.

Because i thought that would be good idea to have variable sampling rate for different
modes of operation i just did a quick hack by setting the dividers const at any rate to
output close to 12.288 Mhz. But then i guess the I2S hardware will not function correctly
- when i run my software implemented DDS process to output a sine wave (0-4000 Hz)
i need to setup sampling frequency of 48 kHz as input of the frequency formula while the
codec is running at 8 kHz.

So it seems i need to set I2S hardware to run at correct sampling rate and same time have
constant output clock to feed the codec. Is this mode of operation possible or i do the
whole thing in a wrong way. Any help to clear my confusion will be appreciated. Thanks

Regards, Chris