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I2C Algorithm. STM32F2 version

Question asked by Michurin on Nov 16, 2012
All my information is based on RM0033 Doc ID 15403 Rev 5 11/2012.
1. Start will be issued after setting by writing START bit to I2C_CR1 register CR1(START)
as soon as SR2(BUSY) is cleared? The document says only Repeated start. If so when did STAT happen? 
2. Master writes Slave address into I2C_DR. Will be SR1(TXE) and SR1(BTF) set simultaneously? Or  SR1(TXE) will set instantly while SLA is transmitting?
3. Does anyone has timing diagram representing I2C_SR1 & I2C_SR2 behavior? 

PS Sorry to say so but this is one of the most confusing manuals I've seen for decades of experience...