AnsweredAssumed Answered

memory with long write recovery time with FSMC of STM32F407IG

Question asked by steveK on Nov 9, 2012
Latest reply on Dec 10, 2013 by hrnic.asmir
Hello,

I want to use a Everspin MRAM MR256A08BCMA35 with the STM32F407IG.
This memory needs a stable address after write or chip enable goes high for at least 12 ns.
My STM and the FSMC are running with a HCLK of 168 MHz = 1 / 5,95 ns, so it holds the address stable after write enable goes high for 1 HCLK = 5,95 ns.
Is there any way to hold the address stable after write access for longer than 1 HCLK cycle.
The only way I found was to slow down HCLK, but this is no solution, because the CPU also gets slower.

Edit:
Could the Bus Turn Around Duration in register FSMC_BTR be a possibility?
The ref. manual says: "These bits are written by software to add a delay at the end of a write/read transaction. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ)"
But there is no timing diagram or any further edescription, so I do not know, if the address is held until NEx goes low again.
Also the durations tEHEL and tEHQZ could not be found anywhere else in the ref. manual or the datasheet.

Outcomes