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Advanced-control timers (TIM1&TIM8) Center-aligned mode (up/down counting)

Question asked by jbougher on Nov 8, 2012
Latest reply on Nov 13, 2012 by jbougher
Evaluating the STM32F207 for a project.

I need to create a triangle waveform, starting from an arbitrary point between two limits, and it needs to be able to start in both incrementing or decrementing fashion. I intend to use DMA to play this waveform out to a DAC

I am looking at Advanced-control timers (TIM1&TIM8) Center-aligned mode (up/down counting), I understand that this only works between 0 and TIMx_ARR but I can offset the waveform to the correct point

From the manual page 297 I understand that
“In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1”
and that
“In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.”

This indicates to me that when the mode is set the Counter register (TIMx_CNT) is cleared and the DIR direction bit is set to increment.

Question
1>Can the Counter register (TIMx_CNT) be loaded to an arbitrary value after the mode is set if the waveform needs to increment
2>If the waveform needs to start decrementing, could the TIMx_ARR register be set to a small value the timer run until the the limit is hit (now in the right state). Timer disabled (Bit 0 CEN: Counter enable). Then the TIMx_ARR and the Counter register (TIMx_CNT) register set to the proper value, and then reenabled

Thanks in advance
Joe

From the manual
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Advanced-control timers (TIM1&TIM8)

Page 297

Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload
value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.

In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.

Page 329

Bits 6:5 CMS[1:0]: Center-aligned mode selection
….
….
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1)

Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.
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