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Event Register workaround for M3

Question asked by dwalker on Oct 25, 2012
For Cortex-M3 processors, there is a bug that prevents the event register from being set on interrupt entry or exit. This can cause problems if an interrupt occurs in an event loop before the WFE instruction is executed. The problem exhibits itself as increased latency if there is a periodic timer interrupt or the event loop hangs. The ST eratta (at least for the STM32L15x) suggests running a timer to produce a timeout event to wakeup the core. This differs from the ARM errata on the same issue (563915) that states the SEV instruction may be issued from within the ISR to set the event flag that should have been done upon exception entry and exit. In my opinion, the ARM suggestion is a better one and I wanted to document this for other users in the group.

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