The 7 requests from the peripherals (TIMx[2,3,4,6,7], ADC1, SPI[1,2], I2Cx[1,2], USARTx[1,2,3]) and DAC Channelx[1,2] are simply logically ORed before entering the DMA, this means that only one request must be enabled at a time. Refer to Figure 25: DMA request mapping.
Can someone help me understand what this means? It sounds like it is saying that only a single peripheral can have DMA enabled at any one time. That seems like a terrible restriction. It makes more sense that only one peripheral that is directed to a particular DMA channel can be enabled at once. And the figure cited shows 7 OR gates, 1 for each channel. That makes more sense, but it is not what the text says! Can someone confirm that the 'sensible' meaning is true?