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STM32F4 - SDIO_CK not stable at 48Mhz

Question asked by Nordicoder on Oct 4, 2012
Latest reply on Oct 4, 2012 by Nordicoder
I want to read/write data from an sd card in high speed 4-bit mode. However the SDIO_CK seems to be wrong when I set the bypass bit to run it at 48MHz ( from PLL48CLK ).

Every seventh/eigth cycle is way to long, with a period of 110ns as apposed to 20ns (which is 50Mhz).

I notice this difference at 400KHz and 25Mhz as well, but it so small it is still within the clocking of data signals.

I have checked with a logic analyzer and the CMD signal is clocked out at 50MHz, but I assume the sd card cannot clock the data in once the CLK signal is "hanging"(and the CMD data is still being clocked out)


Does anyone have some ideas or comments on this? I have tested this on two different STM32F4 mcu's(totally different hardware as well) and the glitch in SDIO_CK is quite the same on both chips.

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