AnsweredAssumed Answered

48/72mhz, PLL*6/PLL*9, with source code

Question asked by blasser.peter on Sep 28, 2012
Latest reply on Sep 30, 2012 by Clive One
Hi, first of all thanks for reading this! 
This is assembly code (gnu arm) for setting up the ST32F103 to make sound out the DAC.  It works in 48mhz PLL mode, but not in 72.  What follows is the complete program, demonstrating the problem.  Thanks again, -Peter B, RTOS engineer, shbobo.net

01.    .thumb                 
02.    .syntax unified
03.    .equ STACKINIT, 0x2000C000
04.    .equ RCC_CR, 0x40021000
05.    .equ RCC_CFGR, 0x40021004
06.    .equ RCC_APB1ENR, 0x4002101C
07.    .equ GPIOA_CRL, 0x40010800
08.    .equ DAC_BOUNDARY, 0x40007400
09.    .equ DAC_DHR12R1, 0x40007408
10. 
11.@for ST32F103RCT6, uses pin PA4 (DAC)
12.@compiled with arm-elf-as or arm-linux-gnueabi-as
13.@-mcpu=cortex-m3 upload with ST-LINK_CLI.exe
14.@>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
15.@the following program sets up an external crystal
16.@at 8 megahertz, then sets up the PLL to multiply.
17.@it thus works at 48 megahertz (*6), and produces a saw
18.@waveform at the DAC output, done by the loop at the end.
19.@this is a distillation of a much larger program that at 48mhz,
20.@works with USB, adc, timer, dac, SYstick, and GPIO. 
21.@but not at 72 mhz.
22.@the question is, if you comment out the following equate,
23.@why does it break at 72 megahertz (*9)???? please,
24.@comment/uncomment the next line about "FORTYEIGHT"
25.    .equ FORTYEIGHT, 1
26.     
27.vectors:       
28.    .word STACKINIT        
29.    .word initiate + 1     
30.    .word initiate + 1
31.    .word initiate + 1
32.    .word initiate + 1
33.    .word initiate + 1
34.    .word initiate + 1
35.     
36..macro LODESTRA reg, val
37.    ldr r1, =\reg @for setting
38.    ldr r0, =\val @configurations
39.    str r0, [r1]  @in Mister ST
40..endm
41. 
42.initiate:
43.    LODESTRA RCC_CR, 0x00010081 @ HSEON
44. 
45.CRYSTAL_waiter:
46.    ldr r1, = RCC_CR
47.    ldr r1, [r1]
48.    ldr r0, = 0x00020002 @ HSERDY
49.    tst r1, r0
50.    beq CRYSTAL_waiter
51.     
52.@NOTE THE FOLLOWING TWO POSSIBLE CONFIGURATIONS
53..ifdef FORTYEIGHT
54.    .equ CLOCKCONFIG, 0x0051FC00
55.    @analyzed in bits:
56.    @xxxx reserved
57.    @x000 MCO off
58.    @x101 USBPRE/1, PLL*6
59.    @0001 PLL*6, HSE as source
60.    @1111 ADC=AHB/8 APB2=AHB/16
61.    @1100 APB1=AHB/2
62.    @0000 0000
63..else
64.    .equ CLOCKCONFIG, 0x001DFD00
65.    @analyzed in bits:
66.    @xxxx reserved
67.    @x000 MCO off
68.    @x001 USBPRE/1.5, PLL*9
69.    @1101 PLL*9, HSE as source
70.    @1111 ADC=AHB/8 APB2=AHB/16
71.    @1101 APB1=AHB/4
72.    @0000 0000
73..endif
74. 
75.    LODESTRA RCC_CFGR, CLOCKCONFIG
76.    LODESTRA RCC_CR, 0x01010081 @PLL ON
77.     
78.PLL_waiter:
79.    ldr r1, = RCC_CR
80.    ldr r1, [r1]
81.    ldr r0, = 0x02020002 @PLL RDY
82.    tst r1, r0
83.    beq PLL_waiter
84. 
85.    LODESTRA RCC_CFGR, (CLOCKCONFIG | 2) @ USE PLL as clock
86.    LODESTRA RCC_APB1ENR, 0x20000000 @ DAC APB1 enable
87.    LODESTRA GPIOA_CRL, 0x44004444 @ analog in for DAC
88.    LODESTRA DAC_BOUNDARY, 0x00010001 @ turn on both DACs
89.1:
90.    ldr r1, = DAC_DHR12R1 
91.    strh r0, [r1]
92.    subs r0, r0, 1
93.    b 1b @loop a saw waveform forever!
94.    .end

Outcomes