We are working on a STM32F417VGTx. We wrote a DMA driver and confirmed it was working memory to memory.
Next, we began integrating it with an SPI driver (SPI2). Initially, the engineer working on the SPI driver was unable to get any transfers going. Then, we revisited the Table 20 in the reference manual, which we didn't realize in our initial reviews, seems to indicate that peripherals are mapped to specific Channel/Stream combinations.
The usage of channels had been a little unclear to us. The reference manual (018909 Rev 1) just says that this is an "example" table and that actual connections will depend on product implementation. This left us asking a lot of questions: Does this mean specific derivatives have different maps? Where are they documented? Is this a software configuration? Is this a microcontroller configuration? Is this “hard-coded” in the silicon?
So, after reviewing the table again, we started using DMA 1, Channel 0 Streams 3 and 4 for SPI3 and made some progress: We are able to perform TX only (stream 4), simultaneous RX and TX (streams 3 and 4), but not RX only (stream 3).
1) Does this in any way ring a bell for someone on something obvious we might be missing?
2) Table 20 indicates that there are 2 channel 0 streams for SPI3_RX and 2 channel 0 streams for SPI3_TX. Is that correct?
3) Table 20 indicates that Channel 2 Stream 2 and Channel 3 Stream 3 are both mapped to I2S2_EXT_RX. Is that correct?