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STM32F10x peripheral driver bug

Question asked by rigo.mate.002 on Sep 9, 2012
Latest reply on Sep 11, 2012 by Clive One
I found the following bug.
I have a 16MHz crystal on my board design. I use the STM32F103RB uC with Atollic True Studio Lite 3.2.

The stm32f10x.h advises me to set the HSE_VALUE according to my crystal. So I set it to16000000. 
In the system_stm32f10x.c file I uncommented the following line:
#define SYSCLK_FREQ_72MHz  72000000
It is supposed to the set the system clock to 72MHz, but as you can see in the SetSysClockTo72 function in the system_stm32f10x.c file:
/*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
                                    RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
It does not care about the defined HSE_VALUE value. It just assumes that the crystal value is 8MHz. Now if I want a correctly initialized 72MHz system I have to uncomment the following line:
#define SYSCLK_FREQ_36MHz  36000000
I think this is a big bug. Or at least it should be mentioned in the readme section of either file.
Any ideas where there is a bugzilla or something similar?

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