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STM32F4 Bit Set Reset Register

Question asked by John F. on Aug 31, 2012
Latest reply on Sep 3, 2012 by John F.
The file stm32f4xx.h defines the BSRR as two 16 bit "halves".

typedef struct
{
  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x24-0x28 */
} GPIO_TypeDef;

The Ref. Manual says the BSRR bits, "can be accessed in word, half-word or byte mode.".

Can I just declare,

__IO uint32_t BSRR;    /*!< GPIO port bit set/reset register,  Address offset: 0x18      */

to write 32 bits in one write? Anyone done this?

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