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STM32 bootload problem

Question asked by lombardini.luca on Aug 24, 2012
Latest reply on Aug 24, 2012 by Clive One
Hi all,

I have this problem:
When I download my firmware on the discovery EVM (using ST-link) eve1rything goes right and when I power up again the board (after a power-off) the firwmare is present.
When I do the same thing on my hardware using JTAG and Jlink tool everything goes right when the board is power. When I turn on the board after a power down nothing happens (I turn on some led to indicate the firmware is running) and I have to connect the board at jtag and reload the firmware to run it again.
Can someone help me?

Thanks,
Luca Lombardini

P.S Here the IAR log when my hardware is connected to Jlink:
Fri Aug 24, 2012 15:30:15: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.4\arm\config\flashloader\ST\FlashSTM32F4xxx.mac
Fri Aug 24, 2012 15:30:16: JLINK command: ProjectFile = C:\arm\Progetti\MECFES II (V10.0) step 2\settings\MECFES_II_Debug.jlink, return = 0
Fri Aug 24, 2012 15:30:16: Device "STM32F407VG" selected (1024 KB flash, 128 KB RAM).
Fri Aug 24, 2012 15:30:16: DLL version: V4.50l, compiled Jul  9 2012 15:02:49
Fri Aug 24, 2012 15:30:16: Firmware: J-Link ARM V8 compiled Jun 19 2012 11:29:30
Fri Aug 24, 2012 15:30:16: JTAG speed is initially set to: 32 kHz
Fri Aug 24, 2012 15:30:16: TotalIRLen = 9, IRPrint = 0x0011
Fri Aug 24, 2012 15:30:16: TotalIRLen = 9, IRPrint = 0x0011
Fri Aug 24, 2012 15:30:17: Found Cortex-M4 r0p1, Little endian.
Fri Aug 24, 2012 15:30:17: TPIU fitted.
Fri Aug 24, 2012 15:30:17: ETM fitted.
Fri Aug 24, 2012 15:30:17: FPUnit: 6 code (BP) slots and 2 literal slots
Fri Aug 24, 2012 15:30:17: Found Cortex-M4 r0p1, Little endian.
Fri Aug 24, 2012 15:30:17: TPIU fitted.
Fri Aug 24, 2012 15:30:17: ETM fitted.
Fri Aug 24, 2012 15:30:17: FPUnit: 6 code (BP) slots and 2 literal slots
Fri Aug 24, 2012 15:30:17: Hardware reset with strategy 0 was performed
Fri Aug 24, 2012 15:30:17: Initial reset was performed
Fri Aug 24, 2012 15:30:17: Found 2 JTAG devices, Total IRLen = 9:
Fri Aug 24, 2012 15:30:17:  #0 Id: 0x4BA00477, IRLen:  4, IRPrint: 0x1 CoreSight JTAG-DP
Fri Aug 24, 2012 15:30:17:  #1 Id: 0x06413041, IRLen:  5, IRPrint: 0x1 STM32 Boundary Scan
Fri Aug 24, 2012 15:30:18: 712 bytes downloaded (3.72 Kbytes/sec)
Fri Aug 24, 2012 15:30:18: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.4\arm\config\flashloader\ST\FlashSTM32F4xxx.out
Fri Aug 24, 2012 15:30:18: Target reset
Fri Aug 24, 2012 15:30:18: Downloaded C:\arm\Progetti\MECFES II (V10.0) step 2\Debug\Exe\SPI Discovery.out to flash memory.
Fri Aug 24, 2012 15:30:18: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.4\arm\config\debugger\ST\Trace_STM32F4xx.dmac
Fri Aug 24, 2012 15:30:18: Found Cortex-M4 r0p1, Little endian.
Fri Aug 24, 2012 15:30:18: TPIU fitted.
Fri Aug 24, 2012 15:30:19: ETM fitted.
Fri Aug 24, 2012 15:30:19: FPUnit: 6 code (BP) slots and 2 literal slots
Fri Aug 24, 2012 15:30:19: Hardware reset with strategy 0 was performed
Fri Aug 24, 2012 15:30:19: 14232 bytes downloaded into FLASH (14.14 Kbytes/sec)
Fri Aug 24, 2012 15:30:19: Loaded debugee: C:\arm\Progetti\MECFES II (V10.0) step 2\Debug\Exe\SPI Discovery.out
Fri Aug 24, 2012 15:30:19: Found Cortex-M4 r0p1, Little endian.
Fri Aug 24, 2012 15:30:19: TPIU fitted.
Fri Aug 24, 2012 15:30:19: ETM fitted.
Fri Aug 24, 2012 15:30:19: FPUnit: 6 code (BP) slots and 2 literal slots
Fri Aug 24, 2012 15:30:19: Hardware reset with strategy 0 was performed
Fri Aug 24, 2012 15:30:19: Target reset

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