AnsweredAssumed Answered

8 bit write on 16 bit wide ext SRAM using NBL0/1

Question asked by h.brad on Aug 21, 2012
Latest reply on Nov 12, 2013 by Amel N
Hello,

I am have been using an external SRAM with the STM32F207. The SRAM I am using is the Cypress CY62167EV30, a 16-Mbit ( 1M x 16 / 2M x 8 ).

The SRAM is used to store a captured image and allow for manipulations to be made.

I tried about a year ago to address all 2MB of the SRAM with 8bit read and writes which I could not get to work. It seemed when I wrote to address 0x6000 0000 the byte was 'copied' to location 0x6010 0000 (1MB).

I have now switched from a monochrome sensor to a color sensor which requires 3x the amount of memory when converted to 24bitRGB format.

Strangely enough, I have been able to address the entire contents of the SRAM by switching to 16bit wide data in the FSMC initialization.

The true question to this post is, why when using the NBL0/1 pins I cannot do 8bit writes the the SRAM. It seems no problem when doing the 8bit read - even from a non 16bit boundary.

Unfortunately I am using BGA parts and it is nearly impossible to throw the NBL pins on a scope, but I loaded the same initialization code into the STM3220g eval board and seen the NBL pins toggling as expected.

Does anyone have any experience with this issue or have any ideas?

Currently I am doing 8bit reads fine, but when writing 8bits I am reading from the upper/lower byte (depending which which is being written) to preserve the data on 16 bit boundaries.

From a hardware standpoint: A0-A19, D0-D15, NBL0/1 ( High/Low Byte Enable ), Chip Enable, Write Enable, Output Enable.

All pins are tied to the FSMC AF and all peripheral clocks are enabled.
Here is my FSMC initialization(minus the pin initialization):

    /*-- FSMC Configuration ------------------------------------------------------*/
    p.FSMC_AddressSetupTime      = 2;
    p.FSMC_AddressHoldTime       = 1;
    p.FSMC_DataSetupTime         = 4;
    p.FSMC_BusTurnAroundDuration = 1;
    p.FSMC_CLKDivision           = 0;
    p.FSMC_DataLatency           = 0;
    p.FSMC_AccessMode            = FSMC_AccessMode_A;

    FSMC_NORSRAMInitStructure.FSMC_Bank               = FSMC_Bank1_NORSRAM1;
    FSMC_NORSRAMInitStructure.FSMC_DataAddressMux     = FSMC_DataAddressMux_Disable;
    FSMC_NORSRAMInitStructure.FSMC_MemoryType         = FSMC_MemoryType_SRAM;
    FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth    = FSMC_MemoryDataWidth_16b;
    FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode    = FSMC_BurstAccessMode_Disable;
    FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait   = FSMC_AsynchronousWait_Disable; 
    FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
    FSMC_NORSRAMInitStructure.FSMC_WrapMode           = FSMC_WrapMode_Disable;
    FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive   = FSMC_WaitSignalActive_BeforeWaitState;
    FSMC_NORSRAMInitStructure.FSMC_WriteOperation     = FSMC_WriteOperation_Enable;
    FSMC_NORSRAMInitStructure.FSMC_WaitSignal         = FSMC_WaitSignal_Disable;
    FSMC_NORSRAMInitStructure.FSMC_ExtendedMode       = FSMC_ExtendedMode_Disable;
    FSMC_NORSRAMInitStructure.FSMC_WriteBurst         = FSMC_WriteBurst_Disable;
    FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
    FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct     = &p;

    FSMC_NORSRAMInit ( &FSMC_NORSRAMInitStructure );

Thanks for reading, and I look forward to any feedback.

Thanks,
Brad

Outcomes