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SPI transactions of greater than 16 bits

Question asked by gti20 on Aug 16, 2012
Latest reply on Aug 17, 2012 by malund.erik

I am looking for recommendations as to how best to deal with SPI transactions where the SPI word length is greater than 16 bits.

I intend to use 64 bit transactions from the host PC to my stm32 board. Therefore, I expect the SPI will interrupt 4 times (if the SPI data size is set to 16). Could I create a counter incremented by the interrupt, wait until the count = 4, then process the 64 bits together? This seems to make sense to me but I guess there would be a problem if the counter was to get out of sync with the transactions from the host.

Are there any suggested or more neater methods of dealing with SPI transactions of greater than 16 bits?

Thanks in advance