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[resolved]Can't get SPI clock to stop properly (RXONLY)

Question asked by Alex_rcpilot on Aug 7, 2012
Latest reply on Aug 10, 2012 by Alex_rcpilot
Hi all, I'm having problem stopping the SPI clock in RXONLY mode. 

PB3(SCK) and PB4(MISO) on my STM32F103VBT6 are used to read from a bunch of external shift registers. On-chip resources are allocated as follows:
  Master mode with NSS managed by software and never enters slave mode; 
  two-line RX-only transfers. I/O pins are remapped to PB3 and PB4. (Using SWD and parallel JTAG has been disabled);
  Word length: 8-bits;
  RXDMA enabled, allowing DMA to manage RXNE events;
  No interrupts enabled for SPI module.

  Channel 2 enabled, Direction = SPI1 DR register 8bits -> Memory 8bits;
  Number of bytes to transfer = 22;
  TCIF2 interrupt enabled;

I wouldn't hesitate to paste my code here if it'd help immediately, but to keep the story short, at the moment I'd just like to describe the steps I've taken:

1. Initialize SPI module without enabling SPI1;
2. Initialize DMA module and enable DMA1-CH2;
3. Enable SPI to start transfer;
4. DMA1-CH2 interrupt has been triggered, but SPI1 wouldn't stop sending out SCK unless I add a line specifically to disable SPI1 within the ISR for DMA1-CH2;
5. Read SPI1 DR and clear all related flags. (Even though it might not be neccessary)

Then things start to get more weird: with the added disabling of SPI1, the first transfer would seem right with exactly 22 bytes or at most 23 bytes transfered. But the second time, my oscilloscope shows something like 44 bytes being transfered before DMA1-CH2 interrupt is triggered. I know this because I've made a GPIO flip itself as soon as the program enters DMA1CH2 ISR. When this happens, OVR is set to 1. What could have prevented DMA from generating a TCIF flag right after 22 bytes have been received? 

I've read RM0008 Rev.11, consulting 
Fig. 244, 
Section - 24.3.8 Disabling the SPI, 
Section 24.3.9 - SPI communication using DMA.

The manual only highlights precautions for disabling SPI during receive-only transfers. Precise timing is required to prevent corruption of the last transfer, or sending more garbage SCK signals after the last useful clock cycle. 

But the manual didn't say whether SCK would stop itself in DMA mode after all bytes have been transferred. I had decided to try and I found that it doesn't stop. Are my findings wrong?

How should I configure these modules to minimize software intervention? I need some clues, thanks.