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STM32F102 and NVIC

Question asked by pjascol on Jul 27, 2012
Latest reply on Jul 30, 2012 by pjascol

I have read the core documents on the NVIC and it says that you can have a mix of pre emption priority and sub priority, for example you could have 2 pre emption and 6 sub priority levels.
The data sheet for the STM32F105 stated that you can have 16 priority levels (4 bits of interrupt of priority are used - this can also be a mix of pre emption and sub priority levels). Which one is correct and if I use the method in the STMF105 data sheet, would I write the interrupt levels to trhe most or least significant nibble of the register i.e. 
NVIC->IPR[PREG_USART2] |= (unsigned long) (0x03 << PBIT_USART2);
NVIC->IPR[PREG_USART2] |= (unsigned long) (0x30 << PBIT_USART2);
to set up Uart to as interrupt level 3