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NVIC interupt nesting and the SCB->ICSR register

Question asked by Jack Peacock on Jul 16, 2012
I use the ICSR register inside an interrupt service routine to determine which vector was used.  I use the low 9 bits to identify the currently active interrupt.

I'm not clear on what happens to the ICSR if nested interrupts are used and a higher priority interrupt occurs immediately after the lower priority service routine starts.  Does the ICSR return to the lower priority vector after the higher priority service routine exits?

For instance, PVD is at priority 1, ADC 1 DMA at priority 6, and TIM8 at priority 12.  Am I always guaranteed that any time I read the ICSR register it will report the matching interrupt vector, even if TIM8 routine is preempted by an ADC DMA and in turn by a PVD request?

I ask because on rare occasions I seem to be getting the wrong vector in the ICSR.  The vector for ADC (vector 25) shows up in DMA 2 stream 4 (vector 67).  Both are set at priority 6.

Processor is an STM32F407 using FreeRTOS and GCC.
  Jack Peacock

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