AnsweredAssumed Answered

Systick, NVIC and how it can go all pear shaped...

Question asked by Nick Smith on Jul 12, 2012
Latest reply on Jan 25, 2016 by foss.neil
Hi, hope someone can help with a little problem I have uncovered in my application.
I am using an STM32F103C8 in a small, custom board. I am not using any library code from any source.

I am using the SYSTICK counter as a 1ms tick, using the interrupt to increment a "coarse" time stamp counter.

I have other interrupts in the system, namely a timer, an SPI and a UART.

Under very specific scenario, ie timer, systick, uart occuring in that order but practically coincident (the systick may occur during the timer I can't tell, but the uart I think is happening afte systick), systick will fire a second time after the uart interrupt has completed. So I get a situation where it appears as thought the coarse time stamp has increment by 2 instead of 1.
The priorities are TIM2 - 0, SPI - 16, UART - 224 and SYSTICK 240 (note STM only uses top 4 bits of NVIC priority registers). I have set preemption/subgroup setting as 7.1 assuming that as STM doesn't use bottom four bits all interruprs can be pre-emptive.

This is very sensitive to timing (ie change optimisation problem goes away etc...)

Any ideas anyone?

BTW it is not enough to just fix this symptom, i need to understand the cause so as to decide on the severity of this bug for devices currently in the field