AnsweredAssumed Answered

STM32F10xx FSMC Wait Signal

Question asked by recht.christoph on Jul 11, 2012
Latest reply on Jul 12, 2012 by recht.christoph
Hello,

in the Document RM0008 (datasheet of the STM32F10xx Family) on Page 510 is the FSMC access described with the external WAIT Signal. It works well for my application now, but i have some problems by understanding the timing issue.

There are two timings in the diagramm: adress phase and data_setup phase. My configuration is Mode B.

Does this mean i can change the length of adress phase with the ADDSET register? Is this also (ADDSET+1)?
Same for the data_setup phase? data_setup phase = (DATASET+1) ?

I'm also confused with the meaning of the max_wait_assertion_time.

Memory asserts the WAIT signal aligned to NOE/NWE which toggles:

data_setup phase >= 4 * HCLK + max_wait_assertion_time

Description:
Where max_wait_assertion_time is the maximum time taken by the memory to assert the

WAIT signal once NEx/NOE/NWE is low.

Is it the time, after NEx/NOE/NWE  ist active, the memory need to bring the WAIT Signal to BUSY level (low) or the maximum time the memory is BUSY(low)?

My first thought was, that the adress phase controls the sample time of the WAIT signal and after the WAIT signal isn't BUSY the data_setup phase begins. But my measurements of the time are not equal to the settings.

Example:
tHCLK = 10ns
DATASET = 4 (+1) = 5

After the WAIT signal isn't BUSY (rising edge) the memory access duration ist about 50ns. But i see it takes 80ns?

Need some more explanation here.

Thanks,
Christoph Recht


Outcomes