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Confusion with the processor architecture

Question asked by amer.sherif on Jun 10, 2012

I've downloaded Sourcery CodeBench the latest version recently as i found it supports processor STM32F100C6.

I set the board to be configured manually and the processor to STM32F100C6, but it didn't work, there was an error with the start-up code, _start definition was missing, otherwise it compiled fine, and couldn't download it to the target.

I changed the board to STMicroelectronics STM32100B-EVAL then the processor is automatically STM32F100VB. No error showed up and downloaded successfully on the target, but once i pause the sequence, i find it stuck at this line

.set  __cs3_isr_wwdg, __cs3_isr_interrupt

in file stm32f10-isrs.S considering that I'm not using the watchdog at all!!

The interrupts i use are:

RTC_IRQHandler

ADC1_IRQHandler

TIM1_UP_TIM16_IRQHandler

TIM2_IRQHandler

and 5 ext interrupts (5-9)

then went to the latter mentioned file and changed every "__cs3_isr_interrupt" with the name of my handler as i thought it'd be the problem of not recognizing the handlers therefore it goes anywhere!

Please take care that in file stm32f10x.h, i uncommented this line #define STM32F10X_LD_VL

Now i checked on the memory mapping located on stm32f10x.h and compared it with the processor's memory from the datasheet, there are some differences on the number of ADCs, timers,...etc For example, my processor has one ADC only unlike what located on the file which can have up to three!

I have no doubt there's something wrong with the processor configuration but couldn't know what exactly it is!!

Any help please?
Thanks in advance!

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