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Synchronized (Chained/Cascaded) Timers

Question asked by cleary.stephen on Jun 6, 2012
Latest reply on Jun 7, 2012 by cleary.stephen
Newbie here...

I'd like to use one timer as a prescaler for another. Both these timers (combined) will act like a single 48-bit "uptime" value, used for timestamping events. The master timer will be driven off APBx.

I have found a ton of info about how to use the timers in complex scenarios, but I couldn't find sufficient information for my (quite simple) needs. I'm familiar with both the STM32F417 Reference Manual and the STM32F4xx Timer Overview documents.

First question: can someone explain the TIMx_SMCR.MSM bit? A timing diagram (with and without) would be a nice addition to the Reference Manual.

We've had race condition problems on our previous platform where, e.g., the "subsecond" counter would roll over before the "second" counter; I'm guessing MSM has something to do with preventing this condition. But it also mentions it "delays" the TRGI; we're planning on running these timers extremely fast, but we can't miss a pulse.

So, if someone could explain the exact semantics of MSM, that would be great.