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Question asked by Luke on May 1, 2012
Latest reply on Sep 20, 2013 by sandrine
I would like to understand what the I2C TRISE register does.

The standard peripheral library effectively sets it to either:
    I2Cx->TRISE = PCLK1 / 1000000 + 1;
    I2Cx->TRISE = (PCLK1/1000000*300)/1000 + 1;  

For example, for a 36MHz peripheral 1 clock, PCLK1=36000000, this results in:
    I2Cx->TRISE = 37;
or for fast mode:
    I2Cx->TRISE = 11;

So, it seems like this can be interpreted as the number of peripheral cycles it takes for the SCL line to go rise.

RM0008 mentions this as well:

The filter value can also be added to TRISE[5:0].

Does anybody know what this means exactly?

I presume that this register somehow affects how many clock cycles the peripheral waits after releasing SCL to see if it has actually gone high (the slave could stretch the clock, so the master needs to verify the line has gone high after some period of time), but I really don't know.  If this is the case, then it seems like you could use TRISE to cause the STM32 to wait a more or less than the I2C spec (300ns for fast, 1000ns for standard) before checking to see that the clock line has indeed gone high.  If you knew your circuit had lower rise times, you could reduce TRISE to reduce some of the bus overhead; conversely, if you knew your bus had higher rise times, you could increase TRISE to make sure that SCL has time to go high.

Has anybody experimented with this setting?