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SRAM with less adress bits - STM32F407IG

Question asked by Neto Godoy on Apr 18, 2012
Latest reply on Apr 21, 2012 by alokm

I'm developing a data acquisition system for a Formula SAE team and the electronic module that I'm designing has a FPGA to acquire multiple digital signals in parallel.

The ideia to read the data stored in the FPGA was to make it look like a SRAM memory, it would have the same functionality and some control and adress bits.

I would like to use the FSMC in SRAM mode with 8 or 16 bits of data and only 3 or 4 bits of adress. Also, I would like to use the other adress bits with other peripherals.

The solution that I came up is to only connect the adress pins that I want to use to the FSMC peripheral and leave the other pins unconnected.

For example, only the [3:0] adress pins would be actually used as adress pins. The [25:4] pins would be internally unconnected to FSMC, but connected to other peripheral of my choice.

Am I missing something or there is no problem with this ideia ?

Thanks and sorry for the bad english!