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ADC Sample Time Selection

Question asked by brown.geoffrey on Apr 10, 2012
Latest reply on Apr 15, 2012 by brown.geoffrey
While it is clear how to configure the ADC sample time, the documentation doesn't provide insight into why one might prefer 239.5 cycles over 13.5 cycles, or the impact of selecting 7.5 cycles (I'm guessing 6 bits of accuracy).

I do understand the sampling theorem so I know why one might choose a sampling rate.  What I'm unclear about is the effect of setting a particular sampling time for the STM32.

Is this documented somewhere ?

Geoffrey

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