AnsweredAssumed Answered

TIM2_CH1_ETR as an external event to clear OCxREF.

Question asked by poppins.mary on Mar 26, 2012
     I'm trying to operate the TIM2_CH1_ETR as an external event to clear OCxREF. I have configured:
1) PA0 as TIM2_CH1_ETR Alternate function and
2) PB11 as TIM2_CH4 PWM output.

I'm trying to implement what is described in Section: 13.3.11 and Fig: 99 from the STM32L Manual. The code is as below. I'm not sure what I'm missing, any help on this will be appreciated.

    TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStruct;
    TIM_OCInitTypeDef TIM_OCInitStructure;

    // Connect TIM2 PWM Output to PB11 pin
    GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_TIM2);
    GPIO_PinAFConfig(GPIOA, GPIO_PinSource0, GPIO_AF_TIM2);

    // Enable Timer2 clock

    // Timer2 Configuration
    TIM_TimeBaseInitStruct.TIM_Prescaler = 0U;
    TIM_TimeBaseInitStruct.TIM_CounterMode = TIM_CounterMode_Up;
    TIM_TimeBaseInitStruct.TIM_Period = 999U;
    TIM_TimeBaseInitStruct.TIM_ClockDivision = TIM_CKD_DIV1;
    TIM_TimeBaseInit(TIM2, &TIM_TimeBaseInitStruct);

    // Output Compare Structure parameters for Duty Cycle
    TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
    TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
    TIM_OCInitStructure.TIM_Pulse = 450U;
    TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
    TIM_OC4Init(TIM2, &TIM_OCInitStructure);

    TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Enable);

    TIM_ARRPreloadConfig(TIM2, ENABLE);
    // ETR_Initilize  
    TIM_ClearOC4Ref(TIM2, TIM_OCClear_Enable);
    TIM_SelectOCREFClear(TIM2, TIM_OCReferenceClear_ETRF);
    TIM_ETRConfig(TIM2, TIM_ExtTRGPSC_OFF, TIM_ExtTRGPolarity_NonInverted, 0);

    TIM_Cmd(TIM2, ENABLE);