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STOne-32: F4 ADC Threshold Reset

Question asked by baird.hal.001 on Jan 13, 2012
My STM32F407 Rev A reset value for the ADC1 watchdog higher threshold value is 0x0000 instead of the documented 0x0FFF. My STM32F103 Rev Y value is 0x0FFF as expected.

The workaround is to set the threshold value before use, which typically happens anyway. An ADC_DeInit will set it to 0xFFF. But, this becomes another item to check compatibility on when migrating from another STM32 processor.

Hmmmmmm. I wonder where all those F's went to ?

Cheers, Hal

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