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Sysclk and USB prescaler Confusion

Question asked by shrestha.durgesh on Dec 5, 2011
Latest reply on Dec 26, 2011 by shrestha.durgesh
My application has a sequencial input data that consist of 128 bytes to be filled in 0,5 ms. So this is obtained by ADC and DMA function for STM32F103. All the data are copied to a buffer in DMA subroutine. The processing of the data(from the buffer) are done in the main function. The rate of data output (i.e. data processing) is slower than the rate of data input to the buffer for the clock summary as clipped in the attached file (it is suggested to see the first few rows of first files and last few rows in the second attachment).
Now the question is, SYSCLCK has to be 72Mhz but it seems it is not so, what could be the reason?
Also as USBPRE is stated as: 'PLL clock is divided by 1' which means 72 Mhz (as PLL is configured as 72 Mhz), but why USB clock is shown as 48 Mhz?
I have understood the codes in the main function should be executed in the frequency of SYSCLK.
So, it would be so nice if someone could solve my confusion.
Thanks in advance.

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