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SDIO and DMA

Question asked by black.paco on Nov 20, 2011
Latest reply on Dec 1, 2011 by Kamenicky.Tomas
When using the SDIO with DMA, the source code should look like this:
(assume that we refer to a read_single_block command)

1.Enable the DataPath state machine;
2.Enable the CommandPath state machine;
3.Check if command response is free of CRC/Timeout errors;
4.Check if command response R1 is free of errors
5.Enable DMA
6. get in a while() loop and wait until the end of the DMA tranfer.

That is the code tha STM Team uses in the evaluation board.

I am woried for the critical session between states 3-5. If you put some
slow code there(for example USART print), an overrun error will occur because
DMA is enabled when the overrun flag is already set.

Yeah, we know that and that is the reason for which we dont put slow codes between
states 3-5. But i am worrying about what will happen if an interrupt happens between this states. If the interrupt routine has to transfer some data via SPI(slow), It will cause an overrun.

So, i decided to enable DMA before i enable the command state machine:
1.Enable the DataPath state machine;
2.Enable DMA
3.Enable the CommandPath state machine;
4.Check if command response is free of CRC/Timeout errors;
5.Check if command response R1 is free of errors
6. get in a while() loop and wait until the end of the DMA tranfer.

Now, if an interrupt happens, it wont cause any overrun because in the worst case
DMA and CPU share the bus with round-robin, so the interrupt and the DMA tranfer
will be running alongside, and hopefully no overrun will occur.

Everything works great, but is this correct? If the FIFO is empty when i enable the DMA, will it tranfer garbage? Or it will wait until there available data in the FIFO?

As i said, i get valid data but i want to be 100% compliant with the specifications.

Thanks,
Nikos

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