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SPI Transfer Less Than 8-bits

Question asked by spaulding.steven on Nov 15, 2011
Latest reply on Nov 16, 2011 by Clive One
I have been reading the SPI documentation for the STM32F4 and it is unclear to me how things function if you have a transfer that is less than 8-bits.

I have a piece of hardware that provides clock and data. There are 132 bits per transfer and new transfers occur approximately every 10us. I cannot change this. It is not clear to me from the documentation what happens after the last 4 clocks. Does the hardware wait 10us and complete the previous transfer with the first 4 bits of the following transfer? Can the receive buffer be read and the internal state reset so that the next transfer starts off looking for a full 8-bits?

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