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FSMC synchronous burst

Question asked by ch on Nov 7, 2011
Latest reply on Nov 11, 2011 by ch
Does anyone have any references for design articles or documentation - beyond the obvious manuals - for operating the FSMC in synchronous burst mode? I have seen AN2784, but this only deals with asynchronous memories.

Specifically, I am trying to design an interface between the STM32F207 and BRAM elements in a Xilinx FPGA. The BRAMs have a synchronous interface which looks a good match for the FSMC in PSRAM mode. I am trying to fill in the time while I wait for my prototype hardware by writing the VHDL to implement this interface in the FPGA, so I cannot as yet experiment with the hardware.

Pages 121 to 126 in the User Manual show the timings for various operations on the synchronous bus. They all show a burst of two accesses. This begs the following questions:

1) Are there always two accesses in burst mode, or can there be just one (eg if a 16-bit write is made to external memory), or more (eg if there is a burst of accesses to adjacent addresses)?

2) What is the function of the byte lane signals in burst mode? They are shown as active in the timing diagrams, so can I assume that the synchronous mode is capable of single byte writes, using a burst length of one, and asserting just one of the byte lane signals?

3) If the number of accesses in a burst is variable, which signal from the STM32 to the memory indicates the end of the burst? All of the control signals (specifically, FSMC_NWE, FSMC_NOE, FSMC_NEx, FSMC_BLN) appear to become inactive one FSMC_CLK cycle too late to perform this function. For a burst of length N they are de-asserted on a clock edge after the one on which the (N+1)th transaction would occur.

Any information gratefully received.