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STM32F4: 64 kB SRAM inaccessible to all peripherals?

Question asked by van_hooft.frank.001 on Nov 3, 2011
Latest reply on Nov 9, 2011 by John F.
We've been looking at the new STM32F4x because we could really use some additional internal memory, and the F4x family advertises up to 192 kB. Sounds great. So today I attended our local STM32F4x roadshow presentation, and in the process got quite the shock. The F4 block diagram showed this juicy big 64 kB SRAM hanging off the processor data bus, and the presenter said this RAM (named the "CCM data RAM") is inaccessible to the DMA controllers or peripherals. He said it can only be accessed by read and write instructions from the processor.

What?? You're kidding right?

Apparently he wasn't kidding, and the F4x datasheet has this to say on the subject:

The 64-Kbyte CCM (core coupled memory) data RAM is not part of the bus matrix (see Figure 1: System architecture). It can be accessed only through the CPU.
I'm sure that ST did this for a reason, and perhaps some people will be dancing in the streets with joy. But for us, where our application involves DMA'ing large amounts of data between various peripherals, that 64 kB of SRAM might as well be located on the moon.

Before we throw in the towel on the F4, I thought I'd throw out a crazy question to this board and ask if anyone knows any different to the above? Is there some way to get data into and out of that block of SRAM without needing to execute load and store software operations for every single word? How do we get data into and out of that big chunk of SRAM in an efficient manner? I'm just hoping there's some trick or piece of information I'm missing here, something that perhaps the presenter today wasn't aware of.

Many thanks.