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F2xx: What can cause an ADC overrun?

Question asked by van_hooft.frank.001 on Sep 9, 2011
Latest reply on Sep 11, 2011 by van_hooft.frank.001
I'm having a lot of trouble with ADC overruns on the F2xx part, and I'm wondering if anyone has any suggestions on what might be going on.

I have the ADC running in "DMA mode 2", dual ADC mode, simultaneous sampling, being triggered by a timer at 8 kHz. I've fed this timer out to an external pin to confirm it's really at 8 kHz. So what's happening is that every 125 uS the two ADCs (ADC1 and ADC2) each take a sample, put their results in the 32-bit ADC_CDR results register, and raise a DMA request.

So far so good, and I can watch the data in the buffer (being written by the DMA) changing as I change the input voltages to the two ADC pins. I've also been able to confirm timing this way as well (by timing how long the buffer fills I can also determine the ADC rate and again confirm 8 kHz).

The ADC does not have a FIFO, so it's critical that its results register be read in time, otherwise an ADC overrun is tripped. The overrun is an unmitigated disaster for the ADC - the overrun logic shuts off the ADC _and_ it shuts off the DMA - it brings everything to a screeching halt, resulting in the complete cessation of ADC data until everything can be re-initialised and started up again. Hence an overrun really needs to be avoided at pretty much all costs.

As far as I can determine (and experiment) the overrun logic cannot be turned off in DMA Mode 2. It can be turned off for a single ADC, but it appears that once you start using the multi-ADC modes such as Mode 2, the "sky is falling" overrun logic becomes enabled by default. If I'm wrong about this, I'd be very happy indeed to hear it.

I've set the priority of the ADC DMA to "Very High", and it's the only DMA in the system with that priority - everything else is either high, medium or low. Hence I'd expect the ADC DMA to have little trouble servicing the ADC. In addition, the DMA is in "double-buffer" mode, so it's always running (unless the ADC overrun turns if off).

Despite this, an overrun happens every 10 or 20 seconds. Obviously something is preventing the ADC DMA from reading the ADC data register quickly enough.

Any ideas what can block or delay a DMA request? What am I missing here?