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STM32F103VET6: How before Interrupt disable flag takes effect?

Question asked by haselwood.don on Aug 16, 2011
Latest reply on Aug 23, 2011 by van_olden.eric
I isolated a "glitch" in a Timer 2 input capture routine--it appears that the actual disabling of the interrupt does not take place until a few cycles following the instruction that disables the interrupts.

Can you point me to a document & section that details the timing?

Below is a snip of the code where the issue was seen--
The intention is to disable interrupts, copy the extended input capture time, a counter incremented by each interrupt, and a counter associated & incremented by RTC interrupts.  After the copying is complete, the Tim2 input capture interrupt (and event udpate for counting overflows) are then re-enabled.

If an interrupt is serviced between the first and second copy instructions, the mainline sees the interrupt count increased, therefore signifying a new input capture, however the first value copied is the old input capture time.  The conclusion must be reached that the interrupts were not disabled.

Removing the re-enable instruction proves that the disable instruction does indeed stop the interrupts, however it does not prove when the interrupt disabling took place.  Placing dummy coded following the instruction that disables the interrupts eliminates the "glitch", thus indicating that the interrupt disabling does not take place immediately, but only after a number of cycles has transpired. 

In this case the processor is running at 48 MHz and APB1 & APB2 at 12 MHz.  One line of thinking is that the TIM2 requires one APB1 cycle (which would be four of the processor cycles).

My finding is empirical and I would like to find some documentation that explains it.



volatile int Tim2_dummy;
struct TIMCAPTRET32 Tim2_inputcapture_ui(void)
{
    struct TIMCAPTRET32 strY;            // 32b input capture time and flag counter

    TIM2_DIER &= ~(TIM_DIER_CC2IE | TIM_DIER_UIE);    // Disable CH2 capture interrupt and counter overflow (p 315)
//    Tim2_dummy += 1;
//    Tim2_dummy += 1;
    __asm__("NOP");            // Wait for event
    __asm__("NOP");            // Wait for event

    strY.ic  = strTim2m.ui[0];            // Get 32b input capture time
    strY.flg = usTim2ch2_Flag;             // Get flag counter
    strY.cnt = uiRTCsystemcounterTim2IC;        // Get RTC_CNT tick counter saved at last input capture
    TIM2_DIER |= (TIM_DIER_CC2IE | TIM_DIER_UIE);    // Enable CH2 capture interrupt and counter overflow (p 315)
   
    return strY;
}

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