AnsweredAssumed Answered

How to get STM32F207 or STM32F217 lowest jitter 50MHz output

Question asked by Moore.Patrick on Jun 22, 2011
Latest reply on Jun 23, 2011 by Moore.Patrick
I have three questions regarding clock configuration for the STM32F207 / STM32F217:

1. Is there any advantage to using any specific HSE frequency between 4MHz and 26MHz that is evenly divisible by 2, if the goal is to divide down to get the PLL input to 2MHz?  (This is assuming I am using a quality low-jitter clock source to begin with.)

2. To get the lowest jitter 50MHz clock for RMII PHY use that can be produced by the STM32F2xx, wouldn't best practice be to feed the 2MHz into the I2SPLL? 

3. Is there any document that shows what the expected jitter performance of the PLL is and how it is expected to vary as the input frequency changes from 1MHz to 2MHz?