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stlink clock rate

Question asked by brown.geoffrey.001 on Oct 13, 2016
I'm curious what the clock rate limits are on the SWD port of the stm32 parts and whether the stlink interfaces can reach these limits.  openocd seems to support changes to the interface speed and will reset the f3discovery board interface to 8Mhz (at least that's what the openocd log seems to indicate).    So in short -- what are the fundamental limits (at the chip level) and how well do the stlink tools do in reaching these limits.