AnsweredAssumed Answered

Hint: DMA and cache coherency

Question asked by jaekel.torsten on Feb 19, 2016
Latest reply on May 8, 2018 by greenwood.greg
To share experience with all:
STM32F7 has DMAs and caches (DCACHE here in mind). You can use a DMA for Peripheral-to-Memory or even Memory-to-Memory (I use as HW-based 'background' memcpy() ).
But you should bear in mind: DMA transfer does not go through MCU DCACHE. It writes directly to memory. If DCACHE is enabled, the same memory location already hosted in cache - any update on memory (done by DMA) is not 'visible' for MCU. MCU will still see the 'old' content because it is read from cache.

It means: DMA is not coherent , they do not force an update on DCACHE
(not a Cache Coherency Interconnect, CCI in the system).

There are some conclusions:
1) before you send something via DMA from memory - a need to do a Cache Clean maintenance operation - force to let update the memory with cache content
2) when something was received in memory via DMA - a need to do Cache Invalidate maintenance operation - force to let update caches again with memory content to see the changes

But, I think there is a faster (and easier way): use the DTCM memory region:
If you manage to have the buffers for DMAs on DTCM then you should be fine: there is not the DCACHE involved, it is tightly coupled for MCU and DMA has dedicated path to it as well.
On this DTCM you will have 'coherency', no need to deal with cache maintenance.
Regular memories with DCACHE 'in between' might look like 'some data missing' (not coherent).

BTW: even the C keyword 'volatile' might be "tricky": it tells compiler not to optimize, to read and update variable all the time again (in order to see the 'side effect'). But it is not related to caches, it is not a cache maintenance operation:
if such a volatile variable is updated by a non-coherent master (DMAs are such one) - the MCU might still not see a new value in it, even volatile used and really read again (but from cache, not memory).
DCACHE in system might need careful consideration what does it mean for specific features such as DMAs.