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L6474 grounding/layout recommendations

Question asked by Maurizio Bianconi on Jun 3, 2014
Latest reply on Jun 25, 2014 by Enrico Poli
The L6474 chip provides three ground pins (PGND, AGND, DGND) as well as a thermal pad (EPAD) connected internally to all three of the above. If I understand the chip's block diagram correctly (datasheet, p. 7), PGND and AGND are tied together within the chip. In the eval board a single ground plane is used for PGND, AGND, DGND and EPAD. In our application it is necessary to avoid coupling of noisy analog currents to the digital domain as well as to the I/O area of the board. Splitting DGND and AGND and using optocouplers may make sense but we need to prevent ground loops. e.g. due to chip-internal connections. Are there any recommendations from your side on this issue?