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SPI Broken Communication

Question asked by atlam.ahmed on Jan 31, 2016
Latest reply on Dec 13, 2017 by Nilesh Patil
Hello,
I am currently evaluating the EVALSTPM34 Smart Metering IC so that a decision can be made about including it in a smart home management system.
Here is the STPM34 IC datasheet for reference: Datasheet check sections 8.5 and 8.6 (pages 65 to 71) for relevant SPI interface information

The design will include a dual core spear processor managing up to 5 STPM34 ICs over SPI using one core and uploading the data simultaneously to a gateway using the other core.

For practical purposes, the SPI interface is being tested using the STM32F407 Discovery board as I have multiples of those lying around for rapid prototyping.
Unfortunately, all attempts to get the SPI interface to produce rational data was in vain.
The only bright side is I am getting consistent, meaningless, but consistent results for every read address.

Major issues can be summarized quickly as follows:

1) The STPM34 tends to send incorrect CRC values for an arbitrary address reads
for example:
addresses 0X04, 0X06 result in an incorrect CRC value (always same data and same CRC value, there is no cross talk involved, data verified using scope)
address 0X08 always results in a CORRECT CRC value  (always same data and same CRC value, there is no cross talk involved,  data verified using scope)

CRC verification was performed using SPI CRC hardware unit of the STM32F047 and using Software function both producing the same results

2)Disabling the CRC byte requires writing a valid 5 Byte transaction 0X24, 0X24, 0X07, 0X00 followed by a CRC of 0X15
The STPM34 doesnt recognize this as a valid transaction and consequently the CRC byte cannot be disabled

3) Disregarding the CRC issues which should only render write operations impossible, all read operations do result in data, however even after a complete power shutdown and restart of the IC,
all data received have nothing to do with default values. This has been tested, with exact similar results on 2 different EVALSTPM34 boards

For your reference here is the initialization code for the SPI interface to verify correct configuration:

void init_SPI(void)
{

GPIO_InitTypeDef GPIO_InitStruct;
SPI_InitTypeDef SPI_InitStruct;

RCC_AHB1PeriphClockCmd(SPI_GPIO_Clock     , ENABLE);
RCC_AHB1PeriphClockCmd(SPI_CRC_Clock     , ENABLE);

GPIO_InitStruct.GPIO_Pin = SPI_MOSI_Pin | SPI_MISO_Pin | SPI_SCL_Pin;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStruct.GPIO_OType = GPIO_OType_PP;
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(SPI_Port, &GPIO_InitStruct);

GPIO_PinAFConfig(SPI_Port, SPI_MOSI_PinSource, SPI_AF);
GPIO_PinAFConfig(SPI_Port, SPI_MISO_PinSource, SPI_AF);
GPIO_PinAFConfig(SPI_Port, SPI_SCL_PinsSource , SPI_AF);

RCC_APB1PeriphClockCmd(SPI_BUS_Clock     , ENABLE);

SPI_InitStruct.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStruct.SPI_Mode = SPI_Mode_Master;    
SPI_InitStruct.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_Low;       
SPI_InitStruct.SPI_CPHA = SPI_CPHA_1Edge;     
SPI_InitStruct.SPI_NSS = SPI_NSS_Soft | SPI_NSSInternalSoft_Set;
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256;
SPI_InitStruct.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStruct.SPI_CRCPolynomial = 263; //--->X8 + X2+X1+X0
SPI_Init(SPIController, &SPI_InitStruct);
SPI_CalculateCRC(SPIController, ENABLE);
SPI_Cmd(SPIController, ENABLE);
}

If possible, can anyone please provide an example of working code that would demonstrate a singe successful read - write - read (reflecting the data change during the write)operation using the std peripheral library for any of the stm32f4 series.
That way I could  be able to verify that the design is valid.

Thank you very much and please let me know if any further case material is required to solve this issue.

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