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Timer interrupts STM32303E-EVAL: Hard fault handler exception

Question asked by cortes.ainhoa on Oct 19, 2015
Latest reply on Oct 19, 2015 by Clive One
Hi,

I'm using OpenSTM32 to debug my application. 

I want to interrupt every 100 usec. In order to do that, I configure an interrupt based on a timer.
First, I evaluated the application in Nucleo-F334R8 and aparently it works fine. 
But, I need to do that in the STM32303E-Eval. So, I tried to evaluate the same code in this board and it does not work, a hard fault exception is produced always.

This is the code:

main.c

01.#include "stm32f30x.h"
02.#include "stm32f30x_it.h"
03.  
04.static unsigned short status = 0;
05.NVIC_InitTypeDef NVIC_InitStructure;
06.TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
07.  
08.int main(void)
09.{
10.    RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
11.    /* Enable timer (timer runs at 10 KHz)*/
12.        //The APB1 bus for timers works at 72 MHz
13.  
14.    TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
15.    TIM_TimeBaseStructure.TIM_ClockDivision = 1;
16.    TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
17.    TIM_TimeBaseStructure.TIM_Period = 3600 - 1;
18.    TIM_TimeBaseStructure.TIM_Prescaler = 2 - 1;
19.    TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
20.    TIM_SelectOutputTrigger(TIM2,TIM_TRGOSource_Update);
21.  
22.    NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
23.    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
24.    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0xF;
25.    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0xF;
26.    NVIC_Init(&NVIC_InitStructure);
27.  
28.    TIM_Cmd(TIM2, ENABLE);
29.  
30.    TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
31.      
32.    while (1)
33.    {
34.        while(status==0) {};
35.        status=0;
36.    }
37.}
38.  
39.void TIM2_IRQHandler(void) {
40.        TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
41.        status=1;
42.         //nothing to do here except for possibly copying DMA buffers of previous conversion
43.}

This is part of the clocks configuration:

01.........
02.static void SetSysClock(void)
03.{
04.  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
05.  
06./******************************************************************************/
07./*            PLL (clocked by HSE) used as System clock source                */
08./******************************************************************************/
09.  
10.  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
11.  /* Enable HSE */
12.  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
13.   
14.  /* Wait till HSE is ready and if Time out is reached exit */
15.  do
16.  {
17.    HSEStatus = RCC->CR & RCC_CR_HSERDY;
18.    StartUpCounter++;
19.  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
20.  
21.  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
22.  {
23.    HSEStatus = (uint32_t)0x01;
24.  }
25.  else
26.  {
27.    HSEStatus = (uint32_t)0x00;
28.  }
29.  
30.  if (HSEStatus == (uint32_t)0x01)
31.  {
32.    /* Enable Prefetch Buffer and set Flash Latency */
33.    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
34.   
35.     /* HCLK = SYSCLK / 1 */
36.     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
37.         
38.     /* PCLK2 = HCLK / 1 */
39.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
40.       
41.     /* PCLK1 = HCLK / 2 */
42.    //This is the Timer 2 clock and I think that it is 36 MHz x 2 = 72 MHz
43.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
44.  
45.    /* PLL configuration */
46.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
47.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
48.  
49.    /* Enable PLL */
50.    RCC->CR |= RCC_CR_PLLON;
51.  
52.    /* Wait till PLL is ready */
53.    while((RCC->CR & RCC_CR_PLLRDY) == 0)
54.    {
55.    }
56.      
57.    /* Select PLL as system clock source */
58.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
59.    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
60.  
61.    /* Wait till PLL is used as system clock source */
62.    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
63.    {
64.    }
65.  }
66.  else
67.  { /* If HSE fails to start-up, the application will have wrong clock
68.         configuration. User can add here some code to deal with this error */
69.  }
70.}
71.........

I don't know why the hard fault exception is produced in this simple example...I have tried with different timers, but it occurs the same...

If you have any suggestion, I would be very grateful.

Thank you!!

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