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Problem in Working Multi channel ADC-1 and ADC-3 Parallely

Question asked by a.surender on Aug 7, 2015
Latest reply on Aug 7, 2015 by Clive One
Hi,

     I am using two Multi channel ADC's (Controller used is STM103RCT6).
 ADC_1(Multi channel as IN4, IN5, IN6) with DMA1 channel-1 and ADC_3 (Multi channel as IN1, IN2, IN3) with DMA2 channel-5, for capturing the  ADC Signals , I am facing a problem when both the DMA's are used parallely,. i.e. i am able to read ADC1 value through DMA1 channel-1, but unable to read ADC3 value using DMA2 channel-5. I am not facing any problem when using either of ADC 1 or ADC 3 standalone. so i kindly request you to help me with this issue at the earliest .I have attached configuration code in text format. Kindly look in to it ASAP.

/* ADC1 DMA1 and ADC3 DMA2 Configuration*/

void ADC1_DMA1_conf()
{
     RCC->APB2ENR               |=     0x001;           // AFIO clk
     RCC->AHBENR                    |=     0x01;           // Enable DMA1 peripheral clock (DMA1 has Channel 1 to 7)
     RCC->AHBENR                    |=     0x02;           // Enable DMA2 peripheral clock (DMA2 has Channel 1 to 5)
     RCC->APB2ENR               |=     0x8200;       // enabling the ADC1 clk and ADC3 clk
     RCC->APB2ENR               |=     0x0000004;      // enabling the GPIOA clk
     GPIOA->CRL                     =     0x000000;   // (GPIOA->CRH&0XFFFFF00F);      // USART1 TX and Rx enable
     AFIO->MAPR                     =     0x0;            // Mapped as ADC
     
     DMA1_Channel1->CPAR           =     (int)&ADC1->DR;      // PERIPHERAL dress
     DMA1_Channel1->CMAR           =     (int)&ADC1_value;      // memory address
     DMA1_Channel1->CNDTR      =     3;                         // number of Data to transfer
     DMA1_Channel1->CCR            =     (0xFFEF & DMA1_Channel1->CCR) | 0x00;     // DMA1_READ_FROM_PERI     (Read from peripheral)
     DMA1_Channel1->CCR           =     (0xFFDF & DMA1_Channel1->CCR) | 0x20;     // DMA1_CIRCULAR_MODE_ENABLED
     DMA1_Channel1->CCR            =     (0xFFBF & DMA1_Channel1->CCR) | 0x00;     // DMA1_PERIPHERAL_INC_MODE_DISABLED (Peripheral increment mode disabled)
     DMA1_Channel1->CCR            =     (0xFF7F & DMA1_Channel1->CCR) | 0x80;     // DMA1_MEMORY_INC_MODE_ENABLED     
     DMA1_Channel1->CCR         |=     0x100;                     // PERIPHERAL size (16-bits)
     DMA1_Channel1->CCR         |=     0x2000;                // priority (High)
     DMA1_Channel1->CCR            =     (0xF3FF & DMA1_Channel1->CCR) | 0x400; //DMA1_MEMORY_SIZE (16BIT)
     DMA1_Channel1->CCR          |=     0x02;                     // transfer Complete INT


     ADC1->CR1                     =     0x100;          // SCAN_MODE_ENABLE 
     ADC1->CR2                    |=     0x00001;     // ENABLE_START     ADC on
     ADC1->CR2                    |=     0x2;              // continue conversion
     ADC1->CR2                    |=     0x100;        // ADC1_DMA_MODE_ENABLE     
     ADC1->CR2                    |=     0xE0000;        // start conversion STRT
     ADC1->CR2                    |=     0x00100000; // ADC1_CONV_ON_EXT_EVENT
     ADC1->CR2                    |=     0x400000;     // #define ADC1_START_REGU_CONV      
     ADC1->SQR1                     =     0x200000;      // ADC1_CHANNEL_SEQ_LENGTH               
     ADC1->SQR3                     =     0x18A4;      // channel in4, in5, in6
     NVIC->ISER[0]               |=     0x0800;           // DMA_CHANNEL1_NVIC_ENABLE
     ADC1->CR2                    |=     0x70000;        // Start conversion of regular channels,Start conversion of injected channels,External trigger conversion mode for regular channels
     DMA1_Channel1->CCR          |=     0x01;           // channel enable
}


void ADC3_DMA2_conf()
{
     DMA2_Channel5->CPAR           =     (int)&ADC3->DR;      // PERIPHERAL dress
     DMA2_Channel5->CMAR           =     (int)&ADC3_value;      // memory address
     DMA2_Channel5->CNDTR      =     3;                         // number of Data to transfer
     DMA2_Channel5->CCR            =     (0xFFEF & DMA2_Channel5->CCR) | 0x00;     // DMA1_READ_FROM_PERI     (Read from peripheral)
     DMA2_Channel5->CCR           =     (0xFFDF & DMA2_Channel5->CCR) | 0x20;     // DMA1_CIRCULAR_MODE_ENABLED
     DMA2_Channel5->CCR            =     (0xFFBF & DMA2_Channel5->CCR) | 0x00;     // DMA1_PERIPHERAL_INC_MODE_DISABLED (Peripheral increment mode disabled)
     DMA2_Channel5->CCR            =     (0xFF7F & DMA2_Channel5->CCR) | 0x80;     // DMA1_MEMORY_INC_MODE_ENABLED     
     DMA2_Channel5->CCR         |=     0x100;                     // PERIPHERAL size (16-bits)
//     DMA2_Channel5->CCR         |=     0x2000;                // priority (High) //////
     DMA2_Channel5->CCR         |=     0x0000;                // priority (low)
     DMA2_Channel5->CCR            =     (0xF3FF & DMA2_Channel5->CCR) | 0x400; //DMA1_MEMORY_SIZE (16BIT)
     DMA2_Channel5->CCR          |=     0x02;                     // transfer Complete INT
          
     ADC3->CR1                     =     0x100;          // SCAN_MODE_ENABLE
     ADC3->CR2                    |=     0x00001;     // ENABLE_START     ADC on
     ADC3->CR2                    |=     0x2;              // continue conversion
     ADC3->CR2                    |=     0x100;        // ADC3_DMA_MODE_ENABLE     
     ADC3->CR2                    |=     0xE0000;        // start conversion STRT
     ADC3->CR2                    |=     0x00100000; // ADC2_CONV_ON_EXT_EVENT
     ADC3->CR2                    |=     0x400000;     // #define ADC2_START_REGU_CONV 
     ADC3->SQR1                     =     0x200000;      // ADC2_CHANNEL_SEQ_LENGTH               
     ADC3->SQR3                     =     0xC41;           // channel in1, in2, in3     
//     ADC3->CR1                     =     0x00;          // channel 0 is selected ///////
     NVIC->ISER[1]               |=     0x0800;           // DMA2_CHANNEL5_NVIC_ENABLE     
     ADC3->CR2                    |=     0x70000;        // Start conversion of regular channels,Start conversion of injected channels,External trigger conversion mode for regular channels
     DMA2_Channel5->CCR          |=     0x01;           // channel enable
}




Regards
surender A

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