The I2S2 and I2S3 clocks which can be derived from the system clock (SYSCLK) or the
PLL3 VCO clock (2 × PLL3CLK). This selection is made through the I2SxSRC bit in the
RCC_CFGR2 register. For more information on PLL3 and how to configure the I2S
clock to achieve high-quality audio performance, please refer to Section 23.4.3: Clock
Retrieving data ...